The present invention relates generally to reading of data of a memory device and, more particularly, to a memory device and a reading method which use read evaluation time differently according to the amount of current flowing in a common source line.
A NAND flash memory device which is a kind of memory device, includes a memory cell array, a row decoder and a page buffer. The memory cell array consists of a plurality of word lines extending along rows, a plurality of bit lines extending along columns, and a plurality of cell strings corresponding to the bit lines.
On one side of the memory cell array, the row decoder is coupled to string selection lines, word lines and common source lines. The other side of the memory cell array includes a page buffer coupled to a plurality of bit lines.
Recently, in order to improve the integration degree of such a flash memory, research for a multi level cell allowing one memory cell to store a large amount of data is being actively conducted. The memory cell is called a Multi Level Cell (hereinafter referred to as a MLC).
Each of the flash memory cells of the NAND flash memory device is composed of a current path formed between a source and a drain in a semiconductor substrate, a floating gate formed between isolation films on the semiconductor substrate and a control gate. Furthermore, programming for the flash memory cells is performed by grounding the source/drain regions of the memory cell and the semiconductor substrate, that is, bulk areas, and applying a positive high voltage to the control gate, thereby causing Flower-Nordheim Tunneling (hereinafter referred to as F-N tunneling). The F-N tunneling is a phenomenon in which electrons of the bulk areas are accumulated on the floating gate due to the electronic field of the high voltage applied to the control gate, so that the threshold voltage of the memory cell is increased.
The reading of data stored in the flash memory device is performed by pre-charging bit lines and then pre-charging the detection node of a page buffer (not shown) in a high level after a first initiation has been performed.
Thereafter, a selection signal having a level V1 is input in order to turn on the bit line selection transistor of the bit line selection unit of the page buffer.
Therefore, the selected bit line becomes an electric potential resulting from subtracting a threshold voltage Vt from the voltage V1. Thereafter, the pre-charge voltage applied to the sensing node is turned off, and the bit line selection signal having a level V2 is applied to the selected bit line selection transistor. In this case, when the electric potential of the bit line coupled to a word line is lower than V2−Vt, the bit line selection transistor is turned off, thereby maintaining the detection node at a high level. When the electric potential of the bit line coupled to a word line is higher than V2−Vt, the bit line selection transistor is turned on, thereby causing the electric potential to be changed through charge sharing with the detection node. A time for waiting for a change in the electric potential with the sensing node after the voltage V2 has been applied to the bit line selection transistor is called read evaluation time.
There may be a case in which, during a read operation, the data of the memory cell is not all read during the read evaluation time due to the bouncing of a source line. That is, during continuous execution of read commands, an amount of current flows to a global source line according to the cell strings coupled to the bit lines. In this case, the source line can not be maintained at 0V due to the current flowing in the source line, thereby causing bouncing.
Due to the bouncing, the voltage of the source line is higher than 0V. Thus, there may be a problem in that, when the erased cell is read, the state of the cell may not be accurately read using only the flowing current within the read evaluation time due to the decreased amount of the current of the cell strings.